bibtype L - Prototype, methodology, f. module, software
ARLID 0451807
utime 20240103211340.8
mtime 20151208235959.9
title (primary) (eng) EdkDSP Accelerator IP Evaluation in Vivado 2014.4 Artix7 AC701 board
publisher
pub_time 2015
keyword FPGA
keyword floating-point accelerator
keyword ethernet
keyword Internet of Things
author (primary)
ARLID cav_un_auth*0101120
name1 Kadlec
name2 Jiří
full_dept (cz) Zpracování signálů
full_dept (eng) Department of Signal Processing
department (cz) ZS
department (eng) ZS
institution UTIA-B
full_dept Department of Signal Processing
fullinstit Ústav teorie informace a automatizace AV ČR, v. v. i.
source
url http://sp.utia.cz/index.php?ids=results&id=Utia_EdkDSP_Vivado_2014_4_AC701
cas_special
project
project_id 7H14007
agency GA MŠk
ARLID cav_un_auth*0307160
abstract (eng) This application note describes precompiled Vivado 2014.4 Artix7 designs with the floating point EdkDSP accelerators and examples. The evaluation MicroBlaze SoC design with the AXI-lite bus is based on the Xilinx BIST (build in self-test) provided by Xilinx for the Artix7 AC701 board and the Vivado 2014.4 design flow. The network HW controller is supporting 1Gbit/100Mbit/10Mbit standards with HW DMA and a SW stack based on the lwIP TCP/IP stack library v1.4.1 with Xilinx adapter v2.2. The implementation follows guidelines described in the Xilinx application note XAPP1026. The MicroBlaze processor is controlling 5 EdkDSP floating point accelerators. Each accelerator is organised as 8xSIMD reconfigurable computing data path, controlled by a PicoBlaze6 controller. This evaluation package is provided by UTIA for the Xilinx AC701 board with the 28nm Artix7 xc7a200t-2 device. This application note explains how to install and use the demonstrator on Windows7, (32 or 64 bit) and the Xilinx AC701 development board.
reportyear 2016
RIV JC
inst_support RVO:67985556
permalink http://hdl.handle.net/11104/0253189
confidential S
arlyear 2015
mrcbU10 2015