| bibtype |
L -
Prototype, methodology, f. module, software
|
| ARLID |
0461500 |
| utime |
20240103212449.1 |
| mtime |
20160805235959.9 |
| title
(primary) (eng) |
Full HD HDMI In-Out HW-Accelerated Demos for Zynq System-on-Module TE0720-03-2IF and TE0701-05 Carrier Board |
| publisher |
|
| keyword |
FPGA |
| keyword |
Full HD HDMI video processing |
| keyword |
Zynq System-on-Module |
| author
(primary) |
| ARLID |
cav_un_auth*0101120 |
| full_dept (cz) |
Zpracování signálů |
| full_dept (eng) |
Department of Signal Processing |
| department (cz) |
ZS |
| department (eng) |
ZS |
| full_dept |
Department of Signal Processing |
| name1 |
Kadlec |
| name2 |
Jiří |
| institution |
UTIA-B |
| fullinstit |
Ústav teorie informace a automatizace AV ČR, v. v. i. |
|
| author
|
| ARLID |
cav_un_auth*0101179 |
| full_dept (cz) |
Zpracování signálů |
| full_dept |
Department of Signal Processing |
| department (cz) |
ZS |
| department |
ZS |
| full_dept |
Department of Signal Processing |
| name1 |
Pohl |
| name2 |
Zdeněk |
| institution |
UTIA-B |
| fullinstit |
Ústav teorie informace a automatizace AV ČR, v. v. i. |
|
| author
|
| ARLID |
cav_un_auth*0225749 |
| full_dept (cz) |
Zpracování signálů |
| full_dept |
Department of Signal Processing |
| department (cz) |
ZS |
| department |
ZS |
| full_dept |
Department of Signal Processing |
| name1 |
Kohout |
| name2 |
Lukáš |
| institution |
UTIA-B |
| fullinstit |
Ústav teorie informace a automatizace AV ČR, v. v. i. |
|
| source |
|
| cas_special |
| project |
| ARLID |
cav_un_auth*0306850 |
| project_id |
7H14004 |
| agency |
GA MŠk |
|
| abstract
(eng) |
This application note describes use of an evaluation package with 3 edge detection and 3 motion detection video processing designs on the Trenz TE0701-05 platform with industrial grade Zynq XC7Z020-2I device on System on Module TE0720-03-2I. All demonstrated video processing algorithms have been developed, debugged and tested in Xilinx SDSoC 2015.4 environment. Algorithms have been compiled by Xilinx SDSoC 2015.4 system level compiler (based on the Xilinx HLS compiler) to Vivado 2015.4 projects, and compiled by Vivado 2015.4 to bitstreams. The SW access functions controlling the HW accelerators have been exported to the Xilinx SDK 2015.4 SW projects as static .a libraries for standalone ARM Cortex A9 applications. This application note also describes 4 edge detection algorithms defined in the SDSoC 2015.4 in form, which enables in the SDK 2015.4 the parallel execution of predefined video processing HW paths with C user code on ARM. |
| RIV |
JC |
| reportyear |
2017 |
| permalink |
http://hdl.handle.net/11104/0261352 |
| confidential |
S |
| arlyear |
2016 |
| mrcbU10 |
2016 |
|