| bibtype |
L -
Prototype, methodology, f. module, software
|
| ARLID |
0462857 |
| utime |
20240103212626.1 |
| mtime |
20160921235959.9 |
| title
(primary) (eng) |
Full HD HDMI In-Out HW-Accelerated Demos for Zynq System-on-Module TE0715-03-30-1I and Sundance EMC2-DP-V2 Platform |
| publisher |
|
| keyword |
HW accelerators |
| keyword |
video processing |
| keyword |
Zynq System-on-Module |
| keyword |
PC 104 standard |
| author
(primary) |
| ARLID |
cav_un_auth*0101120 |
| full_dept (cz) |
Zpracování signálů |
| full_dept (eng) |
Department of Signal Processing |
| department (cz) |
ZS |
| department (eng) |
ZS |
| full_dept |
Department of Signal Processing |
| name1 |
Kadlec |
| name2 |
Jiří |
| institution |
UTIA-B |
| fullinstit |
Ústav teorie informace a automatizace AV ČR, v. v. i. |
|
| author
|
| ARLID |
cav_un_auth*0101179 |
| full_dept (cz) |
Zpracování signálů |
| full_dept |
Department of Signal Processing |
| department (cz) |
ZS |
| department |
ZS |
| full_dept |
Department of Signal Processing |
| name1 |
Pohl |
| name2 |
Zdeněk |
| institution |
UTIA-B |
| fullinstit |
Ústav teorie informace a automatizace AV ČR, v. v. i. |
|
| author
|
| ARLID |
cav_un_auth*0225749 |
| full_dept (cz) |
Zpracování signálů |
| full_dept |
Department of Signal Processing |
| department (cz) |
ZS |
| department |
ZS |
| full_dept |
Department of Signal Processing |
| name1 |
Kohout |
| name2 |
Lukáš |
| institution |
UTIA-B |
| fullinstit |
Ústav teorie informace a automatizace AV ČR, v. v. i. |
|
| source |
|
| cas_special |
| project |
| ARLID |
cav_un_auth*0308433 |
| project_id |
7H14005 |
| agency |
GA MŠk |
| country |
BE |
|
| abstract
(eng) |
The application note describes use of an evaluation package with 3 edge detection and 3 motion detection video processing designs on the Sundance EMC2-DP-V2 platform with industrial grade Zynq XC7Z030-1I device on System on Module TE0715-03-30-1I. All demonstrated video processing algorithms have been developed, debugged and tested in Xilinx SDSoC 2015.4 environment for the Sundance EMC2-DP-V2 platform. Algorithms have been compiled by Xilinx SDSoC 2015.4 System level compiler (based on the Xilinx HLS compiler) to Vivado 2015.4 projects, and compiled by Vivado 2015.4 to bitstreams. The SW access functions controlling the HW accelerators have been exported to the Xilinx SDK 2015.4 SW projects as static .a libraries for standalone ARM Cortex A9 applications. Application note also describes 3 edge detection algorithms coded in format supporting user defined ARM C code which is executing in parallel with the video processing HW paths. |
| RIV |
JC |
| reportyear |
2017 |
| permalink |
http://hdl.handle.net/11104/0262362 |
| confidential |
S |
| arlyear |
2016 |
| mrcbU10 |
2016 |
|