bibtype C - Conference Paper (international conference)
ARLID 0479509
utime 20240103214705.5
mtime 20171013235959.9
SCOPUS 85029518519
DOI 10.1007/978-3-319-66284-8
title (primary) (eng) A Survey of Hardware Technologies for Mixed-Critical Integration Explored in the Project EMC2
specification
page_count 13 s.
media_type P
serial
ARLID cav_un_epca*0479508
ISBN 978-3-319-66283-1
ISSN 0302-9743
title Computer Safety, Reliability, and Security : SAFECOMP 2017 Workshops, ASSURE, DECSoS, SASSUR, TELERISE, and TIPS
page_num 127-140
publisher
place Cham
name Springer
year 2017
editor
name1 Tonetta
name2 Stefano
editor
name1 Schoitsch
name2 Erwin
editor
name1 Bitsch
name2 Friedemann
keyword asymmetric multiprocessing
keyword Network-on-Chip
keyword Time-of-Flight sensor
keyword multi-core architectures
author (primary)
ARLID cav_un_auth*0351450
name1 Isakovic
name2 H.
country AT
author
ARLID cav_un_auth*0351451
name1 Grosu
name2 R.
country AT
author
ARLID cav_un_auth*0351452
name1 Ratasich
name2 D.
country AT
author
ARLID cav_un_auth*0101120
name1 Kadlec
name2 Jiří
full_dept (cz) Zpracování signálů
full_dept Department of Signal Processing
department (cz) ZS
department ZS
institution UTIA-B
full_dept Department of Signal Processing
fullinstit Ústav teorie informace a automatizace AV ČR, v. v. i.
author
ARLID cav_un_auth*0101179
name1 Pohl
name2 Zdeněk
full_dept (cz) Zpracování signálů
full_dept Department of Signal Processing
department (cz) ZS
department ZS
institution UTIA-B
full_dept Department of Signal Processing
fullinstit Ústav teorie informace a automatizace AV ČR, v. v. i.
author
ARLID cav_un_auth*0351453
name1 Kerrison
name2 S.
country GB
source
url http://library.utia.cas.cz/separaty/2017/ZS/kadlec-0479509.pdf
cas_special
project
ARLID cav_un_auth*0308433
project_id 7H14005
agency GA MŠk
country BE
abstract (eng) Technologies described in the paper provide hardware solution from architectural level up to the peripheral and application specific hardware. Moreover paper presents extendable multiprocessing hardware platform based on Zynq hybrid SoC, an asymmetric multiprocessing in video processing architecture, Time-of-Flight sensor and image processing architecture, predictable and verifiable Network-on-Chip (NoC), heterogeneous time-triggered NoC architecture, virtual hardware platform, software-driven energy consumption optimization techniques, and time-predictable L1 cache memory. The application of hybrid SoC platforms opposed to COTS multi-core architecture provides multiple benefits and can be seen as a viable bridging solution in the gap between single- and multi-core architectures.
action
ARLID cav_un_auth*0351454
name SAFECOMP 2017 International Conference on Computer Safety, Reliability, and Security
dates 20170912
mrcbC20-s 20170915
place Trento
country IT
RIV JC
FORD0 20000
FORD1 20200
FORD2 20206
reportyear 2018
num_of_auth 15
mrcbC52 4 A hod 4ah 20231122142720.3
presentation_type PR
permalink http://hdl.handle.net/11104/0276750
cooperation
ARLID cav_un_auth*0320258
name Vienna University of Technology
country AT
cooperation
ARLID cav_un_auth*0301841
name University of Bristol
country GB
mrcbC64 1 Department of Signal Processing UTIA-B 20206 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE
confidential S
mrcbT16-s 0.328
mrcbT16-4 Q2
mrcbT16-E Q2
arlyear 2017
mrcbTft \nSoubory v repozitáři: kadlec-0479509.pdf
mrcbU14 85029518519 SCOPUS
mrcbU24 PUBMED
mrcbU34 WOS
mrcbU63 cav_un_epca*0479508 Computer Safety, Reliability, and Security : SAFECOMP 2017 Workshops, ASSURE, DECSoS, SASSUR, TELERISE, and TIPS 978-3-319-66283-1 0302-9743 127 140 Cham Springer 2017 Lecture Notes in Computer Science 10489
mrcbU67 340 Tonetta Stefano
mrcbU67 340 Schoitsch Erwin
mrcbU67 340 Bitsch Friedemann