| bibtype |
L -
Prototype, methodology, f. module, software
|
| ARLID |
0487429 |
| utime |
20240103215717.8 |
| mtime |
20180305235959.9 |
| title
(primary) (eng) |
SW Defined Floating Point 8xSIMD EdkDSP IP Serving for Adaptive Noise Cancellation |
| publisher |
|
| keyword |
SDSoC system level compiler |
| keyword |
HW acceleration |
| keyword |
programmable logic array |
| author
(primary) |
| ARLID |
cav_un_auth*0101120 |
| name1 |
Kadlec |
| name2 |
Jiří |
| full_dept (cz) |
Zpracování signálů |
| full_dept (eng) |
Department of Signal Processing |
| department (cz) |
ZS |
| department (eng) |
ZS |
| institution |
UTIA-B |
| full_dept |
Department of Signal Processing |
| fullinstit |
Ústav teorie informace a automatizace AV ČR, v. v. i. |
|
| author
|
| ARLID |
cav_un_auth*0101179 |
| name1 |
Pohl |
| name2 |
Zdeněk |
| full_dept (cz) |
Zpracování signálů |
| full_dept |
Department of Signal Processing |
| department (cz) |
ZS |
| department |
ZS |
| institution |
UTIA-B |
| full_dept |
Department of Signal Processing |
| fullinstit |
Ústav teorie informace a automatizace AV ČR, v. v. i. |
|
| author
|
| ARLID |
cav_un_auth*0225749 |
| name1 |
Kohout |
| name2 |
Lukáš |
| full_dept (cz) |
Zpracování signálů |
| full_dept |
Department of Signal Processing |
| department (cz) |
ZS |
| department |
ZS |
| institution |
UTIA-B |
| full_dept |
Department of Signal Processing |
| fullinstit |
Ústav teorie informace a automatizace AV ČR, v. v. i. |
|
| source |
|
| cas_special |
| project |
| ARLID |
cav_un_auth*0307160 |
| project_id |
7H14007 |
| agency |
GA MŠk |
| country |
BE |
|
| abstract
(eng) |
This application note and evaluation package describes design of reprogrammable 8xSIMD EdkDSP IP core for the 28nm FDSOI digital designs of the THINGS2DO project. The IP has been designed with support of high level flow and tested on the Zynq all programmable 28nm chip with two Arm A9 processors and programmable logic area. The developed SW API, algorithmic implementation and mapping to the 8xSIMD EdkDSP IP forms a base for the possible subsequent implementations in the 28nm FDSOI technology. |
| RIV |
JC |
| FORD0 |
20000 |
| FORD1 |
20200 |
| FORD2 |
20206 |
| reportyear |
2018 |
| num_of_auth |
3 |
| permalink |
http://hdl.handle.net/11104/0282554 |
| confidential |
S |
| arlyear |
2018 |
| mrcbU10 |
2018 |
|