| bibtype |
L -
Prototype, methodology, f. module, software
|
| ARLID |
0496948 |
| utime |
20240103220948.7 |
| mtime |
20181122235959.9 |
| title
(primary) (eng) |
Compact Zynq System 2017.4 with SW-defined Floating-Point 8xSIMD EdkDSP Accelerator |
| publisher |
|
| keyword |
SDSoC system level compiler |
| keyword |
embedded C compiler |
| keyword |
HW acceleration |
| keyword |
programmable logic array |
| author
(primary) |
| ARLID |
cav_un_auth*0101120 |
| name1 |
Kadlec |
| name2 |
Jiří |
| full_dept (cz) |
Zpracování signálů |
| full_dept (eng) |
Department of Signal Processing |
| department (cz) |
ZS |
| department (eng) |
ZS |
| institution |
UTIA-B |
| full_dept |
Department of Signal Processing |
| fullinstit |
Ústav teorie informace a automatizace AV ČR, v. v. i. |
|
| author
|
| ARLID |
cav_un_auth*0101179 |
| name1 |
Pohl |
| name2 |
Zdeněk |
| full_dept (cz) |
Zpracování signálů |
| full_dept |
Department of Signal Processing |
| department (cz) |
ZS |
| department |
ZS |
| institution |
UTIA-B |
| full_dept |
Department of Signal Processing |
| fullinstit |
Ústav teorie informace a automatizace AV ČR, v. v. i. |
|
| author
|
| ARLID |
cav_un_auth*0225749 |
| name1 |
Kohout |
| name2 |
Lukáš |
| full_dept (cz) |
Zpracování signálů |
| full_dept |
Department of Signal Processing |
| department (cz) |
ZS |
| department |
ZS |
| institution |
UTIA-B |
| full_dept |
Department of Signal Processing |
| fullinstit |
Ústav teorie informace a automatizace AV ČR, v. v. i. |
|
| source |
|
| cas_special |
| project |
| ARLID |
cav_un_auth*0359206 |
| project_id |
737459 |
| agency |
EC |
|
| abstract
(eng) |
This funkcional sample supports three Trenz Electronic Modules (TE0720-03-2IF, TE0720-03-1QF, TE0720-03-14S-1C) and two Trenz Electronic Carrier Boards (TE0703-05 and TE0706-02). The application note describes design of compact HW system based on Zynq all programmable 28nm chip with one or two Arm A9 processors and programmable logic area. System is optimised for Ethernet connected computing nodes serving for industrial automation, local data processing and data communication. The documented HW architecture is one of candidates for wider use within the ECSEL Productive 4.0 project for the edge computing node in the Industry 4.0 solutions. |
| RIV |
JC |
| FORD0 |
20000 |
| FORD1 |
20200 |
| FORD2 |
20206 |
| reportyear |
2019 |
| num_of_auth |
3 |
| mrcbC52 |
4 A hod 4ah 20231122143608.8 |
| permalink |
http://hdl.handle.net/11104/0289572 |
| mrcbC64 |
1 Department of Signal Processing UTIA-B 20206 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE |
| confidential |
S |
| arlyear |
2018 |
| mrcbTft |
\nSoubory v repozitáři: kadlec-0496948.pdf |
| mrcbU10 |
2018 |
|