bibtype J - Journal Article
ARLID 0499963
utime 20240103221349.4
mtime 20190116235959.9
SCOPUS 85059522887
WOS 000455335500006
DOI 10.1007/s11265-018-1424-1
title (primary) (eng) ALMARVI Execution Platform: Heterogeneous Video Processing SoC Platform on FPGA
specification
page_count 13 s.
media_type P
serial
ARLID cav_un_epca*0327766
ISSN 1939-8018
title Journal of Signal Processing Systems for Signal Image and Video Technology
volume_id 91
volume 1 (2019)
page_num 61-73
publisher
name Springer
keyword ALMARVI
keyword OpenCL
keyword pocl
keyword TTA
keyword TCE
keyword rVEX
keyword ZYNQ
author (primary)
ARLID cav_un_auth*0371032
name1 Hoozemans
name2 J.
country NL
author
ARLID cav_un_auth*0371033
name1 Van Straten
name2 J.
country NL
author
ARLID cav_un_auth*0371034
name1 Viitanen
name2 T.
country FI
author
ARLID cav_un_auth*0371035
name1 Tervo
name2 A.
country FI
author
ARLID cav_un_auth*0101120
name1 Kadlec
name2 Jiří
full_dept (cz) Zpracování signálů
full_dept Department of Signal Processing
department (cz) ZS
department ZS
institution UTIA-B
full_dept Department of Signal Processing
fullinstit Ústav teorie informace a automatizace AV ČR, v. v. i.
author
ARLID cav_un_auth*0371036
name1 Al-Ars
name2 Z.
country NL
source
url http://library.utia.cas.cz/separaty/2019/ZS/kadlec-0499963.pdf
source
url https://link.springer.com/article/10.1007%2Fs11265-018-1424-1
cas_special
project
ARLID cav_un_auth*0306850
project_id 7H14004
agency GA MŠk
abstract (eng) The proliferation of processing hardware alternatives allows developers to use various customized computing platforms to run their applications in an optimal way. However, porting application code on custom hardware requires a lot of development and porting effort. This paper describes a heterogeneous computational platform (the ALMARVI execution platform) comprising of multiple communicating processors that allow easy programmability through an interface to OpenCL. The ALMARVI platform uses processing elements based on both VLIW and Transport Triggered Architectures (ρ-VEX and TCE cores, respectively). It can be implemented on Zynq devices such as the ZedBoard, and supports OpenCL by means of the pocl (Portable OpenCL) project and our ALMAIF interface specification. This allows developers to execute kernels transparently on either processing elements, thereby allowing to optimize execution time with minimal design and development effort.
result_subspec WOS
RIV JC
FORD0 20000
FORD1 20200
FORD2 20206
reportyear 2020
num_of_auth 6
mrcbC52 4 A hod 4ah 20231122143742.8
permalink http://hdl.handle.net/11104/0292833
mrcbC64 1 Department of Signal Processing UTIA-B 20206 COMPUTER SCIENCE, HARDWARE & ARCHITECTURE
confidential S
mrcbC86 2 Article Plant Sciences
mrcbC91 A
mrcbT16-e COMPUTERSCIENCEINFORMATIONSYSTEMS|ENGINEERINGELECTRICALELECTRONIC
mrcbT16-j 0.192
mrcbT16-s 0.298
mrcbT16-B 7.909
mrcbT16-D Q4
mrcbT16-E Q4
arlyear 2019
mrcbTft \nSoubory v repozitáři: kadlec-0499963.pdf
mrcbU14 85059522887 SCOPUS
mrcbU24 PUBMED
mrcbU34 000455335500006 WOS
mrcbU63 cav_un_epca*0327766 Journal of Signal Processing Systems for Signal Image and Video Technology 1939-8018 1939-8115 Roč. 91 č. 1 2019 61 73 Springer