bibtype L - Prototype, methodology, f. module, software
ARLID 0507680
utime 20240103222428.3
mtime 20190819235959.9
title (primary) (eng) Video Input/Output IP Cores for TE0820 SoM with TE0701 Carrier and and Avnet HDMI Input/Output FMC Module
publisher
pub_time 2019
keyword system level compiler
keyword HW acceleration
keyword programmable logic array
author (primary)
ARLID cav_un_auth*0225749
name1 Kohout
name2 Lukáš
full_dept (cz) Zpracování signálů
full_dept (eng) Department of Signal Processing
department (cz) ZS
department (eng) ZS
institution UTIA-B
full_dept Department of Signal Processing
fullinstit Ústav teorie informace a automatizace AV ČR, v. v. i.
author
ARLID cav_un_auth*0101120
name1 Kadlec
name2 Jiří
full_dept (cz) Zpracování signálů
full_dept Department of Signal Processing
department (cz) ZS
department ZS
institution UTIA-B
full_dept Department of Signal Processing
fullinstit Ústav teorie informace a automatizace AV ČR, v. v. i.
author
ARLID cav_un_auth*0101179
name1 Pohl
name2 Zdeněk
full_dept (cz) Zpracování signálů
full_dept Department of Signal Processing
department (cz) ZS
department ZS
institution UTIA-B
full_dept Department of Signal Processing
fullinstit Ústav teorie informace a automatizace AV ČR, v. v. i.
source
url http://sp.utia.cz/index.php?ids=results&id=te0820-hio-ho
cas_special
project
ARLID cav_un_auth*0374054
project_id 8A18013
agency GA MŠk
abstract (eng) The functional sample describes video IP cores interfacing a video input and output of the Trenz TE0701-06 carrier board with TE0820-3EG SoM (System on Module based on Xilinx Zynq UltraScale+) and Avnet HDMI Input/Output FMC module. The system is designed with Xilinx Vivado 2018.3 tool (Web Pack edition).
RIV JC
FORD0 20000
FORD1 20200
FORD2 20206
reportyear 2020
num_of_auth 3
inst_support RVO:67985556
permalink http://hdl.handle.net/11104/0298665
confidential S
arlyear 2019
mrcbU10 2019