| bibtype |
L -
Prototype, methodology, f. module, software
|
| ARLID |
0543781 |
| utime |
20240103230005.8 |
| mtime |
20210714235959.9 |
| title
(primary) (eng) |
DTRiMC tool for TE0808-09-EG-ES1 module on TEBF0808 carrier board |
| publisher |
|
| keyword |
System on Chip |
| keyword |
Zynq Ultrascale+ |
| keyword |
microprocessor |
| keyword |
HW accelerated computing |
| keyword |
automation |
| keyword |
Linux Debian Stretch |
| author
(primary) |
| ARLID |
cav_un_auth*0101120 |
| name1 |
Kadlec |
| name2 |
Jiří |
| institution |
UTIA-B |
| full_dept (cz) |
Zpracování signálů |
| full_dept (eng) |
Department of Signal Processing |
| department (cz) |
ZS |
| department (eng) |
ZS |
| full_dept |
Department of Signal Processing |
| fullinstit |
Ústav teorie informace a automatizace AV ČR, v. v. i. |
|
| author
|
| ARLID |
cav_un_auth*0330517 |
| name1 |
Likhonina |
| name2 |
Raissa |
| institution |
UTIA-B |
| full_dept (cz) |
Zpracování signálů |
| full_dept |
Department of Signal Processing |
| department (cz) |
ZS |
| department |
ZS |
| full_dept |
Department of Signal Processing |
| country |
CZ |
| fullinstit |
Ústav teorie informace a automatizace AV ČR, v. v. i. |
|
| source |
|
| cas_special |
| project |
| project_id |
8A18013 |
| agency |
GA MŠk |
| ARLID |
cav_un_auth*0374054 |
|
| abstract
(eng) |
Evaluation package for the Design Time Resource integration of Model Composer DTRiMC tool. It serves for integration of eight 8xSIMD, FP03x8, floating-point, run-time-reconfigurable accelerators for Zynq Ultrascale+ TE0808-09EG-ES1 module on TEBF0808 carrier board. It provides SW projects and two designs containing the HW design bitstreams and API interface for SW developer in form of shared linux libraries. The SW developer can program ARM host application in C and compile by gcc compiler or in C++ and use the g++ compiler. User can use the Xilinx SDK for compilation and debug of provided SW projects on a PC (Linux or Windows 10, 64bit). The “make” utility can be also used for compilation of host applications directly on the embedded Zynq Ultrascale+ ZU09-EG-ES1 system. All designs presented in this evaluation package contain four independent twins of serial connected FP03x8 accelerators in the programmable logic part of the device. The HW data movers supporting the data communication are represented for the SW developer as shared C/C++ library with simple SW API. The API is identical for several alternatives of HW data movers. The evaluation package includes 8xSIMD FP32 accelerators with HW license enabling only restricted number of operations. If these licensed operations are all used, user has to reset complete system. This will enable to use the licensed count of operations again. |
| RIV |
JC |
| FORD0 |
20000 |
| FORD1 |
20200 |
| FORD2 |
20206 |
| reportyear |
2022 |
| num_of_auth |
2 |
| permalink |
http://hdl.handle.net/11104/0320988 |
| confidential |
S |
| arlyear |
2021 |
| mrcbU10 |
2021 |
|