| bibtype |
L -
Prototype, methodology, f. module, software
|
| ARLID |
0547101 |
| utime |
20220320214521.0 |
| mtime |
20211025235959.9 |
| title
(primary) (eng) |
Data Movers in DTRiMC tool for TE0726 03M 07S board |
| publisher |
|
| keyword |
microcontroller |
| keyword |
HW acceleration |
| keyword |
Xilinx Zynq |
| author
(primary) |
| ARLID |
cav_un_auth*0101120 |
| name1 |
Kadlec |
| name2 |
Jiří |
| institution |
UTIA-B |
| full_dept (cz) |
Zpracování signálů |
| full_dept (eng) |
Department of Signal Processing |
| department (cz) |
ZS |
| department (eng) |
ZS |
| full_dept |
Department of Signal Processing |
| fullinstit |
Ústav teorie informace a automatizace AV ČR, v. v. i. |
|
| author
|
| ARLID |
cav_un_auth*0101179 |
| name1 |
Pohl |
| name2 |
Zdeněk |
| institution |
UTIA-B |
| full_dept (cz) |
Zpracování signálů |
| full_dept |
Department of Signal Processing |
| department (cz) |
ZS |
| department |
ZS |
| full_dept |
Department of Signal Processing |
| fullinstit |
Ústav teorie informace a automatizace AV ČR, v. v. i. |
|
| author
|
| ARLID |
cav_un_auth*0225749 |
| name1 |
Kohout |
| name2 |
Lukáš |
| institution |
UTIA-B |
| full_dept (cz) |
Zpracování signálů |
| full_dept |
Department of Signal Processing |
| department (cz) |
ZS |
| department |
ZS |
| full_dept |
Department of Signal Processing |
| fullinstit |
Ústav teorie informace a automatizace AV ČR, v. v. i. |
|
| author
|
| ARLID |
cav_un_auth*0330517 |
| name1 |
Likhonina |
| name2 |
Raissa |
| institution |
UTIA-B |
| full_dept (cz) |
Zpracování signálů |
| full_dept |
Department of Signal Processing |
| department (cz) |
ZS |
| department |
ZS |
| full_dept |
Department of Signal Processing |
| country |
CZ |
| fullinstit |
Ústav teorie informace a automatizace AV ČR, v. v. i. |
|
| source |
|
| cas_special |
| project |
| project_id |
8A18013 |
| agency |
GA MŠk |
| ARLID |
cav_un_auth*0374054 |
|
| abstract
(eng) |
Package for evaluation of data movers with Design Time Resource integration of Model Composer DTRiMC tool. The DTRiMC tool serves for integration AXI-S IPs for Zynq device on TE0726-03M-07S board. Due to the limited size of the PL logic, the AXI-S IPs is simple AXI-Steam 1024x32bit FIFO with AXI-S I/O connected to data movers. The data movers are generated in the DTRiMC tool by the Xilinx SDSoC 2018.2 compiler. The application note serves for description of definition of these data movers and for comparison of basic properties (area used, performance) of these data movers. |
| RIV |
JC |
| FORD0 |
20000 |
| FORD1 |
20200 |
| FORD2 |
20206 |
| reportyear |
2022 |
| num_of_auth |
4 |
| permalink |
http://hdl.handle.net/11104/0323436 |
| confidential |
S |
| arlyear |
2021 |
| mrcbU10 |
2021 |
|