bibtype	L - Prototype, methodology, f. module, software
ARLID	0584491
utime	20240429144419.3
mtime	20240321235959.9
title (primary) (eng)	Compilation of Vitis AI 3.0 models for different configurations of AMD DPUs.
publisher	pub_time 2024
keyword	embedded systems
keyword	edge computing
author (primary)	ARLID cav_un_auth*0101120 name1 Kadlec name2 Jiří institution UTIA-B full_dept (cz) Zpracování signálů full_dept (eng) Department of Signal Processing department (cz) ZS department (eng) ZS full_dept Department of Signal Processing fullinstit Ústav teorie informace a automatizace AV ČR, v. v. i.
author	ARLID cav_un_auth*0101179 name1 Pohl name2 Zdeněk institution UTIA-B full_dept (cz) Zpracování signálů full_dept Department of Signal Processing department (cz) ZS department ZS full_dept Department of Signal Processing fullinstit Ústav teorie informace a automatizace AV ČR, v. v. i.
author	ARLID cav_un_auth*0225749 name1 Kohout name2 Lukáš institution UTIA-B full_dept (cz) Zpracování signálů full_dept Department of Signal Processing department (cz) ZS department ZS full_dept Department of Signal Processing fullinstit Ústav teorie informace a automatizace AV ČR, v. v. i.
author	ARLID cav_un_auth*0330517 name1 Likhonina name2 Raissa institution UTIA-B full_dept (cz) Zpracování signálů full_dept Department of Signal Processing department (cz) ZS department ZS full_dept Department of Signal Processing country CZ fullinstit Ústav teorie informace a automatizace AV ČR, v. v. i.
source	url https://zs.utia.cas.cz/index.php?ids=results&id=6_TE_AI_3_0
cas_special	project project_id 9A23008 agency GA MŠk country CZ ARLID cav_un_auth*0459137 abstract (eng) Tutorial describes how to compile Vitis AI 3.0 models for AMD DPU HW in configurations B512, B1024, B1600 a B4096. RIV JC FORD0 20000 FORD1 20200 FORD2 20206 reportyear 2025 num_of_auth 4 permalink https://hdl.handle.net/11104/0353248 confidential S arlyear 2024