| bibtype |
L -
Prototype, methodology, f. module, software
|
| ARLID |
0617485 |
| utime |
20250313100604.4 |
| mtime |
20250226235959.9 |
| title
(primary) (eng) |
Support for TE0820 Modules in Vitis 2023.2, AI 3.5 SW, AI 3.0 DPUCZDX8G |
| publisher |
|
| keyword |
artificial intelligence |
| keyword |
object detection |
| keyword |
embedded systems |
| keyword |
edge computing |
| keyword |
Vitis AI 3.5 |
| keyword |
AMD-Xilinx |
| keyword |
Zynq UltraScale+ |
| author
(primary) |
| ARLID |
cav_un_auth*0101120 |
| name1 |
Kadlec |
| name2 |
Jiří |
| institution |
UTIA-B |
| full_dept (cz) |
Zpracování signálů |
| full_dept (eng) |
Department of Signal Processing |
| department (cz) |
ZS |
| department (eng) |
ZS |
| full_dept |
Department of Signal Processing |
| fullinstit |
Ústav teorie informace a automatizace AV ČR, v. v. i. |
|
| author
|
| ARLID |
cav_un_auth*0101179 |
| name1 |
Pohl |
| name2 |
Zdeněk |
| institution |
UTIA-B |
| full_dept (cz) |
Zpracování signálů |
| full_dept |
Department of Signal Processing |
| department (cz) |
ZS |
| department |
ZS |
| full_dept |
Department of Signal Processing |
| fullinstit |
Ústav teorie informace a automatizace AV ČR, v. v. i. |
|
| author
|
| ARLID |
cav_un_auth*0225749 |
| name1 |
Kohout |
| name2 |
Lukáš |
| institution |
UTIA-B |
| full_dept (cz) |
Zpracování signálů |
| full_dept |
Department of Signal Processing |
| department (cz) |
ZS |
| department |
ZS |
| full_dept |
Department of Signal Processing |
| fullinstit |
Ústav teorie informace a automatizace AV ČR, v. v. i. |
|
| author
|
| ARLID |
cav_un_auth*0330517 |
| name1 |
Likhonina |
| name2 |
Raissa |
| institution |
UTIA-B |
| full_dept (cz) |
Zpracování signálů |
| full_dept |
Department of Signal Processing |
| department (cz) |
ZS |
| department |
ZS |
| full_dept |
Department of Signal Processing |
| country |
CZ |
| fullinstit |
Ústav teorie informace a automatizace AV ČR, v. v. i. |
|
| source |
|
| cas_special |
| project |
| project_id |
9A23008 |
| agency |
GA MŠk |
| country |
CZ |
| ARLID |
cav_un_auth*0459137 |
|
| abstract
(eng) |
This tutorial describes support for systems based on TE0820 modules - how to design custom HW platform with AMD DPU for Vitis 2023.2 AI 3.5 runtime inference for family of Trenz Electronic modules TE0820 with AMD Zynq Ultrascale+ device. |
| RIV |
JC |
| FORD0 |
20000 |
| FORD1 |
20200 |
| FORD2 |
20206 |
| reportyear |
2025 |
| num_of_auth |
4 |
| permalink |
https://hdl.handle.net/11104/0364820 |
| confidential |
S |
| arlyear |
2024 |
| mrcbU10 |
2024 |
|