| bibtype |
L -
Prototype, methodology, f. module, software
|
| ARLID |
0618749 |
| utime |
20250423143918.1 |
| mtime |
20250408235959.9 |
| title
(primary) (eng) |
TE0950 VersalTM to ArtixTM Communication |
| publisher |
|
| keyword |
AMD Versal AI Edge |
| keyword |
AMD Artix |
| keyword |
Chip2Chip HW IP block |
| author
(primary) |
| ARLID |
cav_un_auth*0225749 |
| name1 |
Kohout |
| name2 |
Lukáš |
| institution |
UTIA-B |
| full_dept (cz) |
Zpracování signálů |
| full_dept (eng) |
Department of Signal Processing |
| department (cz) |
ZS |
| department (eng) |
ZS |
| full_dept |
Department of Signal Processing |
| fullinstit |
Ústav teorie informace a automatizace AV ČR, v. v. i. |
|
| source |
|
| cas_special |
| project |
| project_id |
9A22004 |
| agency |
GA MŠk |
| country |
CZ |
| ARLID |
cav_un_auth*0459135 |
|
| abstract
(eng) |
The TE0950 board from Trenz Electronic has two FPGA devices, AMD Versal™ AI Edge XCVE2302 in role of the main FPGA of the system and AMD Artix™ XC7A35T FPGA as configurable levelshifter/MUX for FMC and other 3.3 V IOs. These two FPGAs have dedicated up to 14 differential pairs to communicate with. This application note describes how to program the FPGAs and how to transfer AXI4 transaction between Versal™ and Artix™.The procedure described in this text is for a reference design from Trenz Electronic for 2023.2.2 tools. |
| RIV |
JC |
| FORD0 |
20000 |
| FORD1 |
20200 |
| FORD2 |
20206 |
| reportyear |
2026 |
| num_of_auth |
1 |
| permalink |
https://hdl.handle.net/11104/0365897 |
| confidential |
S |
| arlyear |
2025 |
| mrcbU10 |
2025 |
|