Ch. Softley

  1. Kadlec Jiří, Albu F., Softley Ch., Matoušek Rudolf, Heřmánek Antonín :  RLS Lattice for Virtex FPGA using 32-bit and 20-bit Logarithmic Arithmetic, ÚTIA AV ČR, (Praha 2001) Research Report 2036 [2001]
  2. Kadlec Jiří, Heřmánek Antonín, Softley Ch., Matoušek Rudolf, Líčko Miroslav :  32-bit Logarithmic ALU for Handel-C 2.1 and Celoxica DK1, ÚTIA AV ČR, (Praha 2001) Research Report 2037 [2001]
  3. Heřmánek Antonín, Kadlec Jiří, Matoušek Rudolf, Líčko Miroslav, Softley Ch. :  Pipelined Logarithmic 32bit ALU for Celoxica DK1, ÚTIA AV ČR, (Praha 2001) Research Report 2034 [2001]
  4. Matoušek Rudolf, Líčko Miroslav, Heřmánek Antonín, Softley Ch. :  Floating-Point-Like Arithmetic for FPGA, ÚTIA AV ČR, (Praha 2001) Research Report 2039 [2001]
  5. Albu F., Kadlec Jiří, Softley Ch., Matoušek Rudolf, Heřmánek Antonín :  Implementation of Normalized RLS Lattice on Virtex, ÚTIA AV ČR, (Praha 2001) Research Report 2040 [2001]
  6. Kadlec Jiří, Matoušek Rudolf, Heřmánek Antonín, Líčko Miroslav, Softley Ch. :  Logarithmic ALU 32-bit for Handel C 2.1 and Celoxica DK1 , Celoxica User Conference. Proceedings, Celoxica, (Abington 2001) , Celoxica User Conference /1./, (Stratford, GB, 02.04.2001-04.04.2001) [2001] Download
  7. Albu F., Kadlec Jiří, Softley Ch., Matoušek Rudolf, Heřmánek Antonín, Coleman J. N., Fagan A. :  Implementation of (Normalised) RLS Lattice on Virtex , Field-Programmable Logic and Applications. Proceedings, p. 91-100 , Eds: Brebner G., Woods R., Springer, (Berlin 2001) Lecture Notes in Computer Science. vol.2147 , International Conference FPL 2001, (Belfast, IE, 27.08.2001-29.08.2001) [2001]
  8. Coleman J. N., Chester E. I., Softley Ch., Kadlec Jiří :  Arithmetic on the European Logarithmic Microprocessor, ÚTIA AV ČR, (Praha 2001) Research Report 2012 [2001]