Roman Bartosinski

  1. Honzík Petr, Bartosinski Roman, Daněk Martin, Kafka Leoš, Kohout Lukáš, Sýkora Jaroslav :  Video Processing: Foreground Recognition in the ASVP Platform , Smart Multicore Embedded Systems, p. 159-175 , Eds: Massimo T., Bertels K., Karlsson S., Pacull F. [2014] Download DOI: 10.1007/978-1-4614-8800-2_9
  2. Bartosinski Roman, Daněk Martin, Kafka Leoš, Kohout Lukáš, Sýkora Jaroslav :  The Architecture and the Technology Characterization of an FPGA-Based Customizable Application-Specific Vector Coprocessor (ASVP) , Smart Multicore Embedded Systems, p. 45-77 , Eds: Massimo T., Bertels K., Karlsson S., Pacull F. [2014] Download DOI: 10.1007/978-1-4614-8800-2
  3. Daněk Martin, Kafka Leoš, Kohout Lukáš, Sýkora Jaroslav, Bartosinski Roman :  UTLEON3: Exploring Fine-Grain Multi-Threading in FPGAs, Springer, (New York 2013) Circuits & Systems [2013] DOI: 10.1007/978-1-4614-2410-9

  1. Matoušek Rudolf, Daněk Martin, Pohl Zdeněk, Bartosinski Roman, Honzík Petr :  Reconfigurable System-on-a-Chip , Syndicated vol.5, 2 (2005), p. 1-3 [2005]

  1. Bartosinski Roman, Daněk Martin, Sýkora Jaroslav, Kohout Lukáš, Honzík P. :  Foreground Detection and Image Segmentation in a Flexible ASVP Platform for FPGAs , Proceedings of the 2012 Conference on Design & Architectures for Signal & Image Processing, p. 375-376 , Eds: Morawiec Adam, Hinderscheit Jinnie , Conference on Design & Architectures for Signal & Image Processing, (Karlsruhe, DE, 23.10.2012-25.10.2012) [2012] Download
  2. Bartosinski Roman, Daněk Martin, Sýkora Jaroslav, Kohout Lukáš, Honzík P. :  Video Surveillance Application Based on Application Specific Vector Processors , Proceedings of the 2012 Conference on Design & Architectures for Signal & Image Processing, p. 248-255 , Eds: Morawiec Adam, Hinderscheit Jinnie , Conference on Design & Architectures for Signal & Image Processing, (Karlsruhe, DE, 23.10.2012-25.10.2012) [2012] Download
  3. Bartosinski Roman, Daněk Martin, Sýkora Jaroslav, Kohout Lukáš :  Foreground Detection and Image Segmentation in a Flexible ASVP Platform for FPGAs, ( 2012) [2012]
  4. Sýkora Jaroslav, Bartosinski Roman, Kohout Lukáš, Daněk Martin, Honzík P. :  Reducing Instruction Issue Overheads in Application-Specific Vector Processors , Proceedings of the 15th Euromicro Conference on Digital System Design, DSD 2012, p. 600-607 , Eds: Niar Smail, 15th Euromicro Conference on Digital System Design, (Cesme, TR, 05.09.2012-08.09.2012) [2012] Download
  5. Sýkora Jaroslav, Kohout Lukáš, Bartosinski Roman, Kafka Leoš, Daněk Martin, Honzík P. :  The Architecture and the Technology Characterization of an FPGA-based Customizable Application-Specific Vector Processor , Proceedings of the 2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, p. 62-67 , Eds: Raik, J. , Stopjaková, V. , Jenihhin, M. , Vierhaus, H., T. , Pleskacz, W. , Ubar, R. , 2012 IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, (Tallinn, EE, 18.04.2012-20.04.2012) [2012] Download DOI: 10.1109/DDECS.2012.6219026
  6. Bartosinski Roman :  The LD-RLS algorithm with directional forgetting implemented on a vector-like hardware accelerator , ICASSP 2011: IEEE International Conference on Acoustics, Speech, and Signal Processing, p. 1657-1660, ICASSP 2011: IEEE International Conference on Acoustics, Speech, and Signal Processing, (Praha, CZ, 22.05.2011-27.05.2011) [2011] Download DOI: 10.1109/ICASSP.2011.5946817
  7. Daněk Martin, Philippe J.-M., Bartosinski Roman, Honzík Petr, Gamrat Ch. :  Self-Adaptive Networked Entities for Building Pervasive Computing Aschitectures , International Conference on Evolvable Systems: From Biology to Harware, 8th International Conference, ICES 2008, p. 94-105 , Eds: Hornby Gregory S., Sekanina Lukáš, Haddow Pauline C., International Conference on Evolvable Systems: From Biology to Harware, 8th International Conference, ICES 2008, (Praha, CZ, 22.09.2008-24.09.2008) [2008] Download
  8. Daněk Martin, Kadlec Jiří, Bartosinski Roman, Kohout Lukáš :  Increasing the Level of Abstraction in FPGA-based Designes , International Conference on Field Programmable Logic and Applications, p. 5-10 , Eds: Kebschull Udo, International Conference on Field Programmable Logic and Applications, (Heidelberg, DE, 08.09.2008-10.09.2008) [2008] Download
  9. Bartosinski Roman :  Processor Expert AutoSAR-Simulink Library, ( 2008) [2008]
  10. Bartosinski Roman :  Knihovna Proseccor Expert-Simulink, ( 2008) [2008]
  11. Bartosinski Roman :  RCCOM - podpora komunikace s kartami s FPGA z prostředí Matlab a Matlab/Simulink, ( 2007) [2007]
  12. Bartosinski Roman, Daněk Martin, Honzík Petr, Kadlec Jiří :  Modelling Self-Adaptive Networked Entities in Matlab/Simulink , Technical Computing Prague 2007, p. 1-8, Technical Computing Prague 2007, (Praha, CZ, 14.11.2007-14.11.2007) [2007]
  13. Stružka P., Waszniowski L., Bartosinski Roman, Bysterský T. :  Design of Control Application Using Processor Expert Blockset , Technical Computing Prague 2007, p. 1-8, Technical Computing Prague 2007, (Praha, CZ, 14.11.2007-14.11.2007) [2007]
  14. Bartosinski Roman, Kadlec Jiří :  Simulation of MCU hardware peripherals , Technical Computing Prague 2007, p. 1-7, Technical Computing Prague 2007, (Praha, CZ, 14.11.2007-14.11.2007) [2007]
  15. Bartosinski Roman, Hanzálek Z., Stružka P., Waszniowski L. :  Integrated Environment for Embedded Control Systems Design , Proceedings of the 21st IEEE International Parallel & Distributed Processing Symposium, p. 1-8, 21st IEEE International Parallel & Distributed Processing Symposium, (Long Beach, US, 26.03.2007-30.03.2007) [2007]
  16. Kadlec Jiří, Bartosinski Roman, Daněk Martin :  Accelerating MicroBlaze Floating Point Operations , Proceedings 2007 International Conference on Field Programmable Logic and Applications (FPL), p. 621-624 , Eds: Bertels Koen, Najjar Walid, Genderen Arjan, Vassiliadis Stamatis, International Conference on Field Programmable Logic and Applications. FPL 2007, (Amsterdam, NL, 27.08.2007-29.08.2007) [2007]
  17. Kafka Leoš, Bartosinski Roman, Daněk Martin :  Accessory Tools for Partial Dynamic Reconfiguration on Xilinx FPGAs, ÚTIA AV ČR, (Praha 2007) [2007]
  18. Bartosinski Roman :  RCCOM knihovna - podpora hardware-in-the-loop simulace na FPGA z prostředí Matalb/Simulink, ÚTIA AV ČR, (Praha 2007) [2007]
  19. Bartosinski Roman, Hanzálek Z., Waszniowski L., Stružka P. :  Processor Expert Enhances Matlab Simulink Facilities for Embedded Software Rapid Development , Emerging Technologies and Factory Automation 2006, p. 1-4, IEEE Conference on Emerging Technologies and Factory Automation 2006, (Prague, CZ, 20.09.2006-22.09.2006) [2006]
  20. Bartosinski Roman, Kadlec Jiří :  Hardware co-simulation with communication server from MATLAB/Simulink , Technical computing Prague 2006. 14th annual conference proceedings, p. 13-20 , Eds: Procházka A., Technical computing Prague 2006 /14./, (Prague, CZ, 26.10.2006) [2006]
  21. Bartosinski Roman, Daněk Martin, Honzík Petr, Matoušek Rudolf :  Dynamic reconfiguration in FPGA-based SoC designs , ACACES 2005. Advanced Computer Architecture and Compilation for Embedded Systems, p. 35-38 , Eds: Bosschere K., HiPEAC Network of Excellence, (Ghent 2005) , ACACES 2005., (L'Aquila, IT, 26.07.2005) [2005]
  22. Bartosinski Roman, Daněk Martin, Honzík Petr, Matoušek Rudolf :  Dynamic reconfiguration in FPGA-based SoC designs , Proceedings of the 8th IEEE Workshop on Designs and Diagnostics of Electronic Circuits nad Systems, p. 129-136 , Eds: Takách G., Hlawiczka A., Sziraj J., University of West Hungary, (Sopron 2005) , IEEE Design and Diagnostics of Electronic Circuits nad Systems Workshop (DDECS 2005) /8./, (Sopron, HU, 13.04.2005-16.04.2005) [2005]
  23. Bartosinski Roman, Daněk Martin, Honzík Petr, Matoušek Rudolf :  Dynamic reconfiguration in FPGA-based SoC designs. Abstract , FPGA 2005 - ACM/SIGDA Thirteenth ACM International Symposium on Field-Programmable Gate Arrays, p. 274 , Eds: Schmidt H., Wilton S., ACM, (Monterey 2005) , FPGA 2005 /13./, (Monterey, US, 20.02.2005-22.02.2005) [2005]
  24. Bartosinski Roman, Stružka P., Waszniowski L. :  Peert-blockset for processor export and matlab/simuling integration , Technical Computing Prague 2005 : 13th Annual Conference Proceedings, p. 1-8 , Eds: Moler C., Procházka A., Walden B., MATLAB 05. Technical Computing Prague 2005, (Praha, CZ, 15.11.2005) [2005]