Milan Tichý
Coleman J. N., Softley C. I., Kadlec Jiří, Matoušek R., Tichý Milan, Pohl Zdeněk, Heřmánek Antonín, Benschop N. F.
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The European Logarithmic Microprocessor
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IEEE Transactions on Computers vol.57, 4 (2008), p. 532-546 [2008]
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Pohl Zdeněk, Tichý Milan
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RLS Lattice Algorithm with Order Probability Evaluation as an Accelerator
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Proceedings 2007 International Conference on Field Programmable Logic and Applications (FPL), p. 774-777
, Eds: Bertels Koen, Najjar Walid, Genderen Arjan, Vassiliadis Stamatis,
International Conference on Field Programmable Logic and Applications. FPL 2007,
(Amsterdam, NL, 27.08.2007-29.08.2007) [2007]
Tichý Milan, Schier Jan, Gregg D.
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FPGA Implementation of Adaptive Filters based on GSFAP using Log Arithmetic
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Proceedings of The 2006 IEEE Workshop on Signal Processing Systems Design and Implementation, p. 342-347
, Eds: Badawy W., Boumaiza S.,
IEEE Workshop on Signal Processing Systems Design and Implementation. 2006,
(Banff, CA, 02.10.2006-04.10.2006) [2006]
Tichý Milan, Schier Jan, Gregg D.
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Efficient Floating-Point Implementation of High-Order (N)LMS Adaptive Filters in FPGA
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Reconfigurable Computing: Architecures and Applications. Proceedings of the Second International Workshop ARC, p. 311-316
, Eds: Bertels K., Cardoso J. M. P., Vassiliadis S.,
The Second International Workshop on Reconfigurable Computing ARC 2006,
(Delft, NL, 01.03.2006-03.03.2006) [2006]
Tichý Milan, Nisbet A., Gregg D.
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GSFAP adaptive filtering using log arithmetic for rescouse-constrained embedded systems
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FPGA 2006. Fourteenth ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, p. 236-236
, Eds: Wilton S., DeHon A.,
FPGA 2006. ACM/SIGDA International Symposium on Field-Programmable Gate Arrays /14./,
(Monterey, US, 22.02.2006-24.02.2006) [2006]
Ozer E., Tichý Milan, Gregg D.
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Automatic customization of embedded applications for enhanced performance and reduced power using optimizing compiler techniques
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Proceedings of the 12th Workshop on Compilers for Parallel Computers. CPC 2006, p. 16-27
, Eds: Arenaz M., Doallo R., Fraguela B.B.,
Workshop on Compilers for Parallel Computers. CPC 2006. /12./,
(A Coruňa, ES, 09.01.2006-11.01.2006) [2006]
Pohl Zdeněk, Schier Jan, Líčko Miroslav, Heřmánek Antonín, Tichý Milan
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Logarithmic arithmetic for real data types and support for Matlab/Simulink based rapid-FPGA-prototyping
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Proceedings of the International Parallel and Distributed Processing Symposium. IPDPS 2003, p. 1-6
, Eds: Werner B.,
IEEE Computer Society Press,
(Los Alamitos 2003)
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IEEE IPDPS 2003,
(Nice, FR, 22.04.2003-26.04.2003) [2003]
Líčko Miroslav, Schier Jan, Tichý Milan, Kühl M.
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MATLAB/Simulink based methodology for rapid-FPGA-prototyping
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Field-Programmable Logic and Applications. Proceedings of the 13th International Conference, p. 984-987
, Eds: Cheung P. Y. K., Constantinides G. A., de Sousa J. T.,
Springer,
(Berlin 2003)
Lecture Notes in Computer Science. vol.2778 ,
Field-Programmable Logic and Applications /13./,
(Lisabon, PT, 01.09.2003-03.09.2003) [2003]
Pohl Zdeněk, Matoušek Rudolf, Kadlec Jiří, Tichý Milan, Líčko M.
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Lattice adaptive filter implementation for FPGA
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FPGA 2003 ACM/SIGDA Eleventh ACM International Symposium on Field-Programmable Gate Arrays, p. 246,
ACM,
(Monterey 2003)
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FPGA 2003,
(Monterey, US, 23.02.2003-25.02.2003) [2003]
Líčko Miroslav, Métais B., Tichý Milan, Matoušek Rudolf
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Extension for Xilinx System Generator - logarithmic arithmetic blockset
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MATLAB 2002. Sborník příspěvků 10. ročníku konference, p. 280-284,
VŠCHT,
(Praha 2002)
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MATLAB 2002,
(Praha, CZ, 07.11.2002) [2002]
Matoušek Rudolf, Tichý Milan, Pohl Zdeněk, Kadlec Jiří, Softley C.
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Logarithmic number system and floating-point arithmetics on FPGA
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Field-Programmable Logic and Applications: Reconfigurable Computing Is Going Mainstream, p. 627-636
, Eds: Glesner M., Zipf P., Renovell M.,
Springer,
(Berlin 2002)
Lecture Notes in Computer Science. vol.2438 ,
International Conference FPL 2002 /12./,
(Montpellier, FR, 02.09.2002-04.09.2002) [2002]
Líčko Miroslav, Tichý Milan, Heřmánek Antonín, Matoušek Rudolf, Pohl Zdeněk
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Prototyping of DSP algorithms on FPGA
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POSTER 2002, p. 2,
FEL ČVUT,
(Praha 2002)
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International Student Conference on Electrical Engineering /6./,
(Praha, CZ, 23.05.2002) [2002]
Kadlec Jiří, Tichý Milan, Heřmánek Antonín, Pohl Z., Líčko M.
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Matlab Toolbox for high-level bit-exact emulation of HandelC VHDL FPGA designs
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Design, Automation and Test in Europe DATE˙02, p. 264
, Eds: Sciuto D., Kloos C. D.,
IEEE,
(Los Alamitos 2002)
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Design, Automation and Test in Europe DATE˙02,
(Paris, FR, 04.03.2002-08.03.2002) [2002]
Matoušek R., Pohl Z., Kadlec Jiří, Tichý Milan, Heřmánek Antonín
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Logarithmic arithmetic core based RLS LATTICE implementation
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Design, Automation and Test in Europe DATE 02, p. 271
, Eds: Sciuto D., Kloos C. D.,
IEEE,
(Los Alamitos 2002)
,
Design, Automation and Test in Europe DATE 02,
(Paris, FR, 04.03.2002-08.03.2002) [2002]
Tichý Milan, Kovář Bohumil
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Parallel factorised algorithms for mixture estimation
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Artificial Neural Nets and Genetic Algorithms. Proceedings, p. 410-413
, Eds: Kůrková V., Neruda R., Kárný M., Steele M. C.,
Springer,
(Wien 2001)
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International Conference on Artificial Neural Networks and Genetic Algorithms /5./,
(Praha, CZ, 22.04.2001-25.04.2001) [2001]